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Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA.

Mahendrakumar GunasekaranKumar RahulSantosh Yachareni
Published in: ISNCC (2021)
Keyphrases
  • hardware implementation
  • field programmable gate array
  • neural network
  • low cost
  • databases
  • high speed
  • information retrieval
  • pattern recognition
  • evolutionary algorithm
  • reconfigurable hardware
  • fpga device