Rakesh Kumar

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 23

Top Topics

Instruction Scheduling

Top Venues

ACM Trans. Comput. Syst.

Publications

Truls Asheim, Magnus Jahre, Rakesh Kumar
CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions. SESAME@EuroSys (2024)
Truls Asheim, Boris Grot, Rakesh Kumar
A Storage-Effective BTB Organization for Servers. HPCA (2023)
Truls Asheim, Boris Grot, Rakesh Kumar
A Storage-Effective BTB Organization for Servers. CoRR (2023)
Odin Ugedal, Rakesh Kumar
Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control. SBAC-PAD (2022)
Truls Asheim, Boris Grot, Rakesh Kumar
A Specialized BTB Organization for Servers. PACT (2022)
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. ACM Trans. Archit. Code Optim. 19 (2) (2022)
Truls Asheim, Tanvir Ahmed Khan, Baris Kasikci, Rakesh Kumar
Impact of microarchitectural state reuse on serverless functions. WOSC@Middleware (2022)
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. CoRR (2022)
Rakesh Kumar, Alejandro Martínez, Antonio Gonzalez
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors. CoRR (2021)
Truls Asheim, Boris Grot, Rakesh Kumar
BTB-X: A Storage-Effective BTB Organization. IEEE Comput. Archit. Lett. 20 (2) (2021)
Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K. Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles A. Pokam, Heiner Litz, Baris Kasikci
Twig: Profile-Guided BTB Prefetching for Data Center Applications. MICRO (2021)
Truls Asheim, Rakesh Kumar, Boris Grot
Fetch-Directed Instruction Prefetching Revisited. CoRR (2020)
Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. HPCA (2020)
Fredrik Strupe, Rakesh Kumar
Uncovering Hidden Instructions in Armv8-A Implementations. HASP@MICRO (2020)
Rakesh Kumar, Boris Grot
Shooting Down the Server Front-End Bottleneck. ACM Trans. Comput. Syst. 38 (3-4) (2020)
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
Freeway: Maximizing MLP for Slice-Out-of-Order Execution. HPCA (2019)
Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. DATE (2019)
Rakesh Kumar, Boris Grot, Vijay Nagarajan
Blasting through the Front-End Bottleneck with Shotgun. ASPLOS (2018)
Rakesh Kumar, José Cano, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio Gonzalez
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation. ISPASS (2017)
Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan
Boomerang: A Metadata-Free Architecture for Control Flow Delivery. HPCA (2017)
Rakesh Kumar, Alejandro Martínez, Antonio González
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. ACM Trans. Comput. Syst. 33 (4) (2016)
José Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio González
Quantitative characterization of the software layer of a HW/SW co-designed processor. IISWC (2016)
Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan
D: Mitigating the NUMA bottleneck via coherent DRAM caches. MICRO (2016)
Rakesh Kumar, Alejandro Martínez, Antonio González
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Rakesh Kumar, Alejandro Martínez, Antonio González
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. HiPC (2013)
Rakesh Kumar, Alejandro Martínez, Antonio González
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. SBAC-PAD (2013)
Rakesh Kumar, Alejandro Martínez, Antonio González
Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. HPCC/EUC (2013)
Rakesh Kumar, Alejandro Martínez, Antonio González
Speculative dynamic vectorization for HW/SW co-designed processors. PACT (2012)