D: Mitigating the NUMA bottleneck via coherent DRAM caches.
Cheng-Chieh HuangRakesh KumarMarco ElverBoris GrotVijay NagarajanPublished in: MICRO (2016)
Keyphrases
- memory access
- main memory
- load balancing
- high density
- execution model
- caching scheme
- external memory
- random access memory
- database management systems
- low voltage
- data structure
- risk management
- cache hit ratio
- instruction set
- shared memory
- parallel processing
- parallel algorithm
- index structure
- distributed systems
- nearest neighbor
- management system