R. Sakthivel

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 7

Top Topics

Top Venues

J. Circuits Syst. Comput.

Int. J. Inf. Comput. Secur.

Int. J. Circuit Theory Appl.

Publications

I. Munavar Sheriff, R. Sakthivel
The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption. IEEE Access 12 (2024)
V. Keerthy Rai, R. Sakthivel
Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations. J. Circuits Syst. Comput. 31 (12) (2022)
Sreejeesh S. G., R. Sakthivel, Jayaraj U. Kidav
Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging. IEEE Access 8 (2020)
V. Keerthy Rai, R. Sakthivel
Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications. J. Circuits Syst. Comput. 29 (12) (2020)
Thirumalesu Kudithi, R. Sakthivel
An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, . Int. J. Circuit Theory Appl. 48 (8) (2020)
Thirumalesu Kudithi, R. Sakthivel
High-performance ECC processor architecture design for IoT security applications. J. Supercomput. 75 (1) (2019)
M. Vanitha, R. Sakthivel, R. Mangayarkarasi, Suvarcha Sharma
Nonlinear System Modelling Using Programmable Hardware for Soft Computing Applications. SocProS (2) (2018)
R. Sakthivel, M. Vanitha, Harish M. Kittur
Low power high throughput reconfigurable stream cipher hardware VLSI architectures. Int. J. Inf. Comput. Secur. 6 (1) (2014)
R. Sakthivel, Harish M. Kittur
Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy. Circuits Syst. Signal Process. 33 (8) (2014)
R. Sakthivel, Harish M. Kittur
Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver. IEICE Electron. Express 10 (12) (2013)
R. Sakthivel, K. Sravanthi, Harish M. Kittur
Low power energy efficient pipelined multiply-accumulate architecture. ICACCI (2012)