Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations.
V. Keerthy RaiR. SakthivelPublished in: J. Circuits Syst. Comput. (2022)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- power saving
- high power
- power dissipation
- low power consumption
- vlsi circuits
- delay insensitive
- wireless transmission
- digital signal processing
- neural network
- vlsi architecture
- logic circuits
- cmos technology
- mixed signal
- image sensor
- gate array
- ultra low power
- real time
- lateral inhibition
- parallel processing
- synaptic weights