Peng Zhang

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 16

Top Topics

High Level Synthesis

Deblocking Filter

Pipeline Architecture

Motion Estimation

Top Venues

Publications

Yukun Zhang, Guoqing Xiang, Chen Li, Peng Zhang, Hao Lin, Wei Yan
A Fast Adaptive Motion Vector Resolution Algorithm for AVS3. ICCE (2024)
Chen Li, Guoqing Xiang, Yukun Zhang, Yan Cui, Peng Zhang, Wei Yan
Bayesian Decision-based Bandwidth Resource Control Optimization Algorithm for Integer-Pixel Motion Estimation in AVS3. ICCE (2024)
Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang, Hao Wang, Yifan Li, Yihang Qiu, Guojie Luo, Huawei Li, Haihua Shen, Mingyu Chen, Dongbo Bu, Wenxing Zhu, Ye Cai, Xiaoming Xiong, Ying Jiang, Yi Heng, Peng Zhang, Bei Yu, Biwei Xie, Yungang Bao
iEDA: An Open-source infrastructure of EDA. ASPDAC (2024)
Hao Lin, Yingbo Wen, Guoqing Xiang, Xinyu Qu, Peng Zhang, Wei Yan
A Fast CTU-level SAO Algorithm and Its Hardware Architecture for AVS3 Video Coding. ICCE (2024)
Xizhong Zhu, Guoqing Xiang, Peng Zhang, Xiaodong Xie
A hardware-friendly algorithm for LCU-level pipe-lined integer motion estimation. Multim. Tools Appl. 83 (3) (2024)
Zhijian Hao, Heming Sun, Guoqing Xiang, Peng Zhang, Xiaoyang Zeng, Yibo Fan
A Reconfigurable Multiple Transform Selection Architecture for VVC. IEEE Trans. Very Large Scale Integr. Syst. 31 (5) (2023)
Shaokang Wang, Xiaofeng Huang, Guoqing Xiang, Xizhong Zhu, Jiaojiao Yang, Peng Zhang, Huizhu Jia, Xiaodong Xie
An Efficient Real-Time Hardware Architecture for Deblocking Filter in AVS3. ICME (2023)
Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. FPGA (2019)
Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong
S2FA: an accelerator automation framework for heterogeneous computing in datacenters. DAC (2018)
Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong
TGPA: tile-grained pipeline architecture for low latency CNN inference. ICCAD (2018)
Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture. CoRR (2018)
Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang
Automated accelerator generation and optimization with composable, parallel and pipeline architecture. DAC (2018)
Young-kyu Choi, Peng Zhang, Peng Li, Jason Cong
HLScope+, : Fast and accurate performance estimation for FPGA HLS. ICCAD (2017)
Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. DAC (2017)
Jason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang
Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper. ISLPED (2016)
Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, Jason Cong
CMOST: a system-level FPGA compilation framework. DAC (2015)
Peng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong
Resource-Aware Throughput Optimization for High-Level Synthesis. FPGA (2015)
Meng Li, Peng Zhang, Chuang Zhu, Huizhu Jia, Xiaodong Xie, Jason Cong, Wen Gao
High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis. ICCE (2015)
Jason Cong, Muhuan Huang, Peng Zhang
Combining computation and communication optimizations in system synthesis for streaming applications. FPGA (2014)
Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. DAC (2014)
Peng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peng Zhang, Peter Maass, Ming Jiang, Jason Cong
FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. FCCM (2014)
Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong
Memory partitioning for multidimensional arrays in high-level synthesis. DAC (2013)
Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong
Polyhedral-based data reuse optimization for configurable computing. FPGA (2013)
Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). FPGA (2013)
Jason Cong, Muhuan Huang, Peng Zhang
Efficient system-level mapping from streaming applications to FPGAs (abstract only). FPGA (2013)
Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong
Memory partitioning and scheduling co-optimization in behavioral synthesis. ICCAD (2012)
Jason Cong, Peng Zhang, Yi Zou
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. DAC (2012)
Jason Cong, Karthik Gururaj, Peng Zhang, Yi Zou
Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. J. Electr. Comput. Eng. 2012 (2012)
Jason Cong, Bin Liu, Raghu Prabhakar, Peng Zhang
A Study on the Impact of Compiler Optimizations on High-Level Synthesis. LCPC (2012)
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
An integrated and automated memory optimization flow for FPGA behavioral synthesis. ASP-DAC (2012)
Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou
Combining module selection and replication for throughput-driven streaming programs. DATE (2012)
Jason Cong, Peng Zhang, Yi Zou
Combined loop transformation and hierarchy allocation for data reuse optimization. ICCAD (2011)