Paul Beckett

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 17

Top Topics

Memory Footprint

Internet And The World Wide Web

Asynchronous Circuits

Top Venues

Publications

Zixin Cai, Xin He, Xin Liu, Shijie Tu, Xinjie Sun, Paul Beckett, Aditya Dubey, Arnan Mitchell, Guanghui Ren, Xu Liu, Xiang Hao
Wavelength-selective wavefront shaping by metasurface. Frontiers Inf. Technol. Electron. Eng. 24 (4) (2023)
Nguyen Le Huy, Paul Beckett
Optimising Power-Performance in SOI-based Null Convention Logic. ICICDT (2022)
Abdur Rahim Mohammad Forkan, Flora Salim, Russell Conduit, Paul Beckett, Stephen R. Robinson
TIARA: technology integrated apnea respiration analyser. UbiComp (2019)
Tayab Din Memon, Aneela Pathan, Paul Beckett
FPGA Based Implementation and Area Performance Analysis of Sigma-Delta Modulated Steepest Algorithm for Channel Equalization. ICSPCS (2018)
Nastaran Nemati, Paul Beckett, Mark C. Reed, Karl M. Fant
Clock-Less DFT-Less Test Strategy for Null Convention Logic. IEEE Trans. Emerg. Top. Comput. 6 (4) (2018)
Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei
A Physical Unclonable Function With Redox-Based Nanoionic Resistive Memory. IEEE Trans. Inf. Forensics Secur. 13 (2) (2018)
Peter J. Radcliffe, Karina Gomez Chavez, Paul Beckett, Justin Spangaro, Conrad Jakob
Usability of LoRaWAN Technology in a Central Business District. VTC Spring (2017)
Andrew Przybylski, Kashfia Haque, Paul Beckett
The Bel array: asynchronous fine-grained reconfigurable co-processing. ACSW (2017)
Leah Heiss, Paul Beckett, Amy Carr-Bottomley
Redesigning the Trans-disciplinary: Working Across Design, Craft and Technological Boundaries to Deliver an Integrated Wearable for Cardiac Monitoring. Conference on Designing Interactive Systems (2016)
Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei
A Physical Unclonable Function with Redox-based Nanoionic Resistive Memory. CoRR (2016)
Nastaran Nemati, Mark C. Reed, Karl M. Fant, Paul Beckett
Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic. ISCAS (2016)
Renuka Sovani, Prashant Dabholkar, Paul Beckett
An asynchronous short word length Delta-Sigma FIR filter for low power DSP. ICSPCS (2016)
Prashant Dabholkar, Renuka Sovani, Paul Beckett
A low latency asynchronous Jenkins hash engine for IP lookup. ISCAS (2016)
Andrew Przybylski, Kashfia Haque, Paul Beckett
The Bel array: An asynchronous fine-grained co-processor for DSP. ICSPCS (2016)
Prashant Dabholkar, Paul Beckett
A high throughput, low latency null convention logic 16×16-bit multiplier. ICSPCS (2016)
Matthew M. Kim, Karl M. Fant, Paul Beckett
Design of asynchronous RISC CPU register-file Write-Back queue. VLSI-SoC (2015)
Kashfia Haque, Conrad Jakob, Paul Beckett
Low Power Spatial Computing Using Null Convention Logic. DSDIS (2015)
Matthew M. Kim, Paul Beckett
Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA. DSD (2014)
Jing Yu, Paul Beckett
A dual-rail LUT for reconfigurable logic using null convention logic. ACM Great Lakes Symposium on VLSI (2014)
Kashfia Haque, Paul Beckett
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Tayab Din Memon, Paul Beckett, Amin Z. Sadik
POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters. J. Signal Process. Syst. 70 (3) (2013)
Paul Beckett, Tayab Din Memon
Reconfigurable Blocks Based on Balanced Ternary. J. Signal Process. Syst. 67 (1) (2012)
Kashfia Haque, Paul Beckett
A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection. VLSI Design (2011)
Kashfia Haque, Paul Beckett
A Radiation Hard Lut Block with Auto-Scrubbing. FPL (2011)
Paul Beckett, Heiko Rudolph
Run. DELTA (2010)
Paul Beckett
Towards a balanced ternary FPGA. FPT (2009)
Paul Beckett
Power scalability in a mesh-connected reconfigurable architecture. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Paul Beckett
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors. IEEE Trans. Very Large Scale Integr. Syst. 16 (2) (2008)
Lianlian Zeng, Paul Beckett
Soft Error Rate Estimation in Deep Sub-micron CMOS. PRDC (2007)
Paul Beckett
Low-power spatial computing using dynamic threshold devices. ISCAS (3) (2005)
Paul Beckett
Low-power circuits using dynamic threshold devices. ACM Great Lakes Symposium on VLSI (2005)
Paul Beckett, S. C. Goldstein
Why area might reduce power in nanoscale CMOS. ISCAS (3) (2005)
Paul Beckett
A Polymorphic Hardware Platform. IPDPS (2003)
Paul Beckett
Exploiting multiple functionality for nano-scale reconfigurable systems. ACM Great Lakes Symposium on VLSI (2003)
Paul Beckett
A fine-grained reconfigurable logic array based on double gate transistors. FPT (2002)