Pablo Abad Fidalgo

Publication Activity (10 Years)

Years Active: 2007-2023
Publications (10 Years): 9

Top Topics

Database Operations

Computational Cost

Memory Hierarchy

Top Venues

IEEE Trans. Parallel Distributed Syst.

Publications

Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
Performance Characterization of Popular DNN Models on Out-of-Order CPUs. PACT (2023)
Alvaro Saiz, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
Top-Down Performance Profiling on NVIDIA's GPUs. IPDPS (2022)
Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking. IEEE Trans. Parallel Distributed Syst. 32 (12) (2021)
Pablo Prieto, Pablo Abad Fidalgo, Jose Angel Herrero, José-Ángel Gregorio, Valentin Puente
SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads. ICPP (2020)
Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation. CoRR (2019)
Adrian Colaso, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. IPDPS (2019)
Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
Mosaic: A Scalable Coherence Protocol. Int. J. Parallel Program. 46 (6) (2018)
Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation. IEEE Trans. Parallel Distributed Syst. 29 (5) (2018)
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory. IEEE Trans. Parallel Distributed Syst. 27 (1) (2016)
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
Improving last level shared cache performance through mobile insertion policies (MIP). Parallel Comput. 49 (2015)
Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs. DSD (2013)
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
Improving coherence protocol reactiveness by trading bandwidth for latency. Conf. Computing Frontiers (2012)
Pablo Abad Fidalgo, Valentin Puente, Lucia G. Menezo, José-Ángel Gregorio
Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate. IEEE Trans. Parallel Distributed Syst. 23 (11) (2012)
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
Balancing Performance and Cost in CMP Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 23 (3) (2012)
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip. ICCD (2012)
Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. NOCS (2012)
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks. HPCA (2009)
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
Reducing the Interconnection Network Cost of Chip Multiprocessors. NOCS (2008)
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto
Rotary router: an efficient architecture for CMP interconnection networks. ISCA (2007)