Nihar Ranjan Mohapatra

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 16

Top Topics

Levenberg Marquardt

Wide Field Of View

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Nishant Kumar, Hari Shanker Gupta, Anuj Srivastava, Nihar Ranjan Mohapatra
A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications. ISCAS (2024)
Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs. VLSID (2024)
Nishant Kumar, Hari Shanker Gupta, Nilesh M. Desai, Nihar Ranjan Mohapatra
Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics. APCCAS (2023)
Shubham Patil, Anand Sharma, Gaurav R, Abhishek Kadam, Ajay Kumar Singh, Sandip Lashkare, Nihar Ranjan Mohapatra, Udayan Ganguly
Process Voltage Temperature Variability Estimation of Tunneling Current for Band-to-Band-Tunneling based Neuron. CoRR (2023)
Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics. VDAT (2022)
Satyajit Mohapatra, Nihar Ranjan Mohapatra
Dispersion in Placement: Quantification and Insights. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Kaushal Kumari Neeraj, Nihar Ranjan Mohapatra
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis. VDAT (2021)
Satyajit Mohapatra, Nihar Ranjan Mohapatra
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD). VLSI Design (2020)
Satyajit Mohapatra, Nihar Ranjan Mohapatra
Gradient Error Compensation in SC-MDACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Amratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra
An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS Transistors. VLSI Design (2019)
Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. VLSI Design (2019)
Sarath Chandran G. M, Mohit D. Ganeriwala, Nihar Ranjan Mohapatra
Capacitance and Surface Potential Model for III-V Double-Gate FET. ISDCS (2019)
Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra
Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS. ISVLSI (2018)
Satyajit Mohapatra, Nihar Ranjan Mohapatra
The HotSpot Compensation in High Speed Data Converters. MWSCAS (2018)
Satyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra
A 64b/66b Line Encoding for High Speed Serializers. VLSI Design (2017)
Jatindeep Singh, Satyajit Mohapatra, Nihar Ranjan Mohapatra
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices. VDAT (2017)