Nanda K. Unnikrishnan

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 12

Top Topics

Directed Acyclic

Adjacency Matrix

Top Venues

IEEE Open J. Circuits Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Nanda K. Unnikrishnan, Joe Gould, Keshab K. Parhi
SCV-GNN: Sparse Compressed Vector-based Graph Neural Network Aggregation. CoRR (2023)
Nanda K. Unnikrishnan, Keshab K. Parhi
InterGrad: Energy-Efficient Training of Convolutional Neural Networks via Interleaved Gradient Scheduling. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (5) (2023)
Nanda K. Unnikrishnan, Joe Gould, Keshab K. Parhi
SCV-GNN: Sparse Compressed Vector-Based Graph Neural Network Aggregation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Nanda K. Unnikrishnan, Keshab K. Parhi
Multi-Channel FFT Architectures Designed via Folding and Interleaving. ISCAS (2022)
Nanda K. Unnikrishnan, Keshab K. Parhi
Multi-Channel FFT Architectures Designed via Folding and Interleaving. CoRR (2022)
Nanda K. Unnikrishnan, Keshab K. Parhi
LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling. ICCAD (2021)
Keshab K. Parhi, Nanda K. Unnikrishnan
Correction to "Brain-Inspired Computing: Models and Architectures". IEEE Open J. Circuits Syst. 2 (2021)
Nanda K. Unnikrishnan, Keshab K. Parhi
LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor Scheduling. CoRR (2021)
Keshab K. Parhi, Nanda K. Unnikrishnan
Brain-Inspired Computing: Models and Architectures. IEEE Open J. Circuits Syst. 1 (2020)
Nanda K. Unnikrishnan, Keshab K. Parhi
A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks. ISCAS (2020)
Nanda K. Unnikrishnan, Mario Garrido, Keshab K. Parhi
Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued Serial FFT. ISCAS (2019)
Mario Garrido, Nanda K. Unnikrishnan, Keshab K. Parhi
A Serial Commutator Fast Fourier Architecture for Real-Valued Signals. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)