Michael M. Oshima

Publication Activity (10 Years)

Years Active: 2005-2011
Publications (10 Years): 0

Publications

Bruce Andrew Doyle, Alvin Leng Sun Loke, Sanjeev K. Maheshwari, Charles Lin Wang, Dennis Michael Fischette, Jeffrey G. Cooper, Sanjeev K. Aggarwal, Tin Tin Wee, Chad O. Lackey, Harishkumar S. Kedarnath, Michael M. Oshima, Gerry R. Talbot, Emerson S. Fang
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. A-SSCC (2011)
Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. ISSCC (2010)
Alvin Leng Sun Loke, Bruce Andrew Doyle, Michael M. Oshima, Wade L. Williams, Robert G. Lewis, Charles Lin Wang, Audie Hanpachern, Karen M. Tucker, Prashanth Gurunath, Gladney C. Asada, Chad O. Lackey, Tin Tin Wee, Emerson S. Fang
processor links. CICC (2009)
Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Michael J. Gilsdorf
A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking. IEEE J. Solid State Circuits 41 (8) (2006)
Alvin Leng Sun Loke, Robert K. Barnes, Tin Tin Wee, Michael M. Oshima, Charles E. Moore, Ronald R. Kennedy, Jim O. Barnes, Robert A. Zimmer, Kari L. Arave, H. Herman M. Pang, Tom E. Cynkar, Aaron M. Volz, Jim R. Pfiester, R. J. Martin, Robert H. Miller, David A. Hood, Gordon W. Motley, Ed J. Rojas, Tom M. Walley, Michael J. Gilsdorf
A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking. CICC (2005)