Marcel Runge

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 20

Top Topics

Error Estimation

Software Defined Radio

Top Venues

Publications

Julius Edler, Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter. VLSI Technology and Circuits (2023)
Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter. IEEE J. Solid State Circuits 58 (8) (2023)
Kai Misselwitz, Marcel Runge, Friedel Gerfers
A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC. ICECS 2022 (2022)
Marcel Runge, Julius Edler, Dario Schmock, Tobias Kaiser, Friedel Gerfers
A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS. CICC (2022)
Enne Wittenhagen, Marcel Runge, Nima Lotfi, Hossein Ghafarian, Yuan Tian, Friedel Gerfers
. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Marcel Runge, Dario Schmock, Tobias Kaiser, Friedel Gerfers
A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS. CICC (2021)
Julius Edler, Marcel Runge, Friedel Gerfers
A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS. MWSCAS (2021)
Marcel Runge, Julius Edler, Tobias Kaiser, Friedel Gerfers
A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS. CICC (2021)
Marcel Runge, Dario Schmock, Enne Wittenhagen, Friedel Gerfers
A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX. ISCAS (2020)
Enne Wittenhagen, Marcel Runge, Wilhelm Keusgen, Friedel Gerfers
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio. ISCAS (2020)
Paul Hollmann, Marcel Runge, Friedel Gerfers
A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network. ICECS (2020)
Friedel Gerfers, Nima Lotfi, Enne Wittenhagen, Hossein Ghafarian, Yuan Tian, Marcel Runge
Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems. ICECS (2019)
Nima Lotfi, Pedro Lehmann Ibáñez, Marcel Runge, Friedel Gerfers
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI. ISCAS (2019)
Marcel Runge, Nima Lotfi, Friedel Gerfers
Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs. ISCAS (2019)
Marcel Runge, Friedel Gerfers
Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise. ISCAS (2018)
Marcel Runge, Sebastian Linnhoff, Friedel Gerfers
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS. MWSCAS (2018)
Nima Lotfi, Marcel Runge, Friedel Gerfers
AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs. MWSCAS (2018)
Marcel Runge, Dario Schmock, Philipp Scholz, Georg Böck, Friedel Gerfers
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS. ESSCIRC (2018)
Marcel Runge, Dario Schmock, Friedel Gerfers
Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC. MWSCAS (2017)
Marcel Runge, Friedel Gerfers
A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters. ISCAS (2017)