M. S. Hrishikesh

Publication Activity (10 Years)

Years Active: 2000-2003
Publications (10 Years): 0

Publications

Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
Static energy reduction techniques for microprocessor caches. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA (2002)
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
Static Energy Reduction Techniques for Microprocessor Caches. ICCD (2001)
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger
Clock rate versus IPC: the end of the road for conventional microarchitectures. ISCA (2000)