Louis Y.-Z. Lin

Publication Activity (10 Years)

Years Active: 2013-2019
Publications (10 Years): 4

Top Topics

Structural Patterns

Shared Memory Multiprocessor

Ordering Heuristics

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Louis Y.-Z. Lin, Charles Chia-Hao Hsu, Charles H.-P. Wen
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings. IEEE Access 7 (2019)
Louis Y.-Z. Lin, Charles H.-P. Wen
Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation. IEEE Access 6 (2018)
Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax? ACM Great Lakes Symposium on VLSI (2017)
Louis Y.-Z. Lin, Charles H.-P. Wen
Speed binning with high-quality structural patterns from functional timing analysis (FTA). ASP-DAC (2016)
Jasper C. C. Chang, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen
TA-FTA: transition-aware functional timing analysis with a four-valued encoding. DAC (2015)
Jerry C. Y. Ku, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen
Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation. ASP-DAC (2014)
Hunta H.-W. Wang, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen
CASTA: CUDA-Accelerated Static Timing Analysis for VLSI Designs. ICPP (2014)
Louis Y.-Z. Lin, Christina C.-H. Liao, Charles H.-P. Wen
Synthesizing multiple scan chains by cost-driven spectral ordering. ASP-DAC (2013)
Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)