Leandro Passetti

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 7

Top Topics

Backpropagation Neural Networks

Reduced Complexity

Analog To Digital Converter

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Int. J. Circuit Theory Appl.

Publications

Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda
Evaluation of the Performance Impact of Clock Jitter and Phase Noise in a Two-Band Frequency-Interleaved ADC. ICECS (2023)
Leandro Passetti, Damián A. Morero, Benjamín T. Reyes, Mario R. Hueda
Adaptive Digital Compensation of Analog Impairments in Frequency Interleaved ADC for Next-Generation High-Speed Communication Receivers. IEEE Access 11 (2023)
Fredy Solis, Álvaro Fernandez Bocco, Agustin C. Galetto, Leandro Passetti, Mario R. Hueda, Benjamin T. Reyes
A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS. Int. J. Circuit Theory Appl. 49 (10) (2021)
Leandro Passetti, Benjamin T. Reyes, Damian A. Morero, Mario R. Hueda
Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. ISCAS (2021)
Leandro Passetti, Agustin C. Galetto, Diego J. Hernando, Damian A. Morero, Benjamin T. Reyes, Mario R. Hueda
Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers. ISCAS (2020)
Benjamin T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda
An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Benjamin T. Reyes, Laura Biolato, Agustin C. Galetto, Leandro Passetti, Fredy Solis, Mario R. Hueda
An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing. LASCAS (2018)