A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS.
Fredy SolisÁlvaro Fernandez BoccoAgustin C. GalettoLeandro PassettiMario R. HuedaBenjamin T. ReyesPublished in: Int. J. Circuit Theory Appl. (2021)
Keyphrases
- analog to digital converter
- nm technology
- low power
- cmos technology
- image sensor
- power consumption
- wireless sensor networks
- cmos image sensor
- random access memory
- high speed
- energy efficient
- sensor networks
- real time
- mixed signal
- energy saving
- design considerations
- sar images
- power dissipation
- parameter estimation
- low cost
- management system
- data streams