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Agustin C. Galetto
ORCID
Publication Activity (10 Years)
Years Active: 2018-2023
Publications (10 Years): 8
Top Topics
Connection Weights
Radial Basis
Delta Sigma
Backpropagation Neural Networks
Top Venues
LASCAS
IEEE Access
IEEE Trans. Circuits Syst. I Regul. Pap.
MWSCAS
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Publications
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Agustin C. Galetto
,
Juan I. Bonetti
,
Benjamín T. Reyes
,
Damián A. Morero
,
Mario R. Hueda
Digital Background Compensation of Analog Impairments in Jointly Frequency-Time Interleaved DACs.
IEEE Access
11 (2023)
Agustin C. Galetto
,
Benjamin T. Reyes
,
Damian A. Morero
,
Mario R. Hueda
Backpropagation Based Background Compensation of TI-DAC Errors in High-Speed Transmitters.
MWSCAS
(2022)
Agustin C. Galetto
,
Benjamin T. Reyes
,
Damian A. Morero
,
Mario R. Hueda
Adaptive Background Compensation of Frequency Interleaved DACs With Application to Coherent Optical Transceivers.
IEEE Access
9 (2021)
Fredy Solis
,
Álvaro Fernandez Bocco
,
Agustin C. Galetto
,
Leandro Passetti
,
Mario R. Hueda
,
Benjamin T. Reyes
A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS.
Int. J. Circuit Theory Appl.
49 (10) (2021)
Agustin C. Galetto
,
Benjamin T. Reyes
,
Damian A. Morero
,
Mario R. Hueda
Background Compensation of Frequency Interleaved DAC for Optical Transceivers.
LASCAS
(2021)
Leandro Passetti
,
Agustin C. Galetto
,
Diego J. Hernando
,
Damian A. Morero
,
Benjamin T. Reyes
,
Mario R. Hueda
Backpropagation-Based Background Compensation of Frequency Interleaved ADC for Coherent Optical Receivers.
ISCAS
(2020)
Benjamin T. Reyes
,
Laura Biolato
,
Agustin C. Galetto
,
Leandro Passetti
,
Fredy Solis
,
Mario R. Hueda
An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
(6) (2019)
Benjamin T. Reyes
,
Laura Biolato
,
Agustin C. Galetto
,
Leandro Passetti
,
Fredy Solis
,
Mario R. Hueda
An 8-bit 3.2GS/S CMOS time-interleaved SAR ADC with non-buffered input demultiplexing.
LASCAS
(2018)