Lars Friebe

Publication Activity (10 Years)

Years Active: 2000-2005
Publications (10 Years): 0

Publications

Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. J. VLSI Signal Process. 41 (1) (2005)
Andreas Dehnhardt, Mark Bernd Kulaczewski, Lars Friebe, Sören Moch, Peter Pirsch, Hans-Joachim Stolberg, Carsten Reuter
A multi-core SoC design for advanced image and video compression. ICASSP (5) (2005)
Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch
HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Comput. Archit. News 32 (3) (2004)
Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE (2003)
Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC (2003)
Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch
HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) (2003)
Stefan Langemeyer, Helge Kloos, Christian Simon-Klar, Lars Friebe, Willm Hinrichs, Hanno Lieske, Peter Pirsch
A compact and flexible multi-DSP system for real-time SAR applications. IGARSS (2003)
Christian Simon-Klar, Lars Friebe, Helge Kloos, Hanno Lieske, Willm Hinrichs, Peter Pirsch
A multi DSP board for real time SAR processing using the HiPAR-DSP 16. IGARSS (2002)
Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch
HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. ICASSP (2002)
Lars Friebe, Yoshikazu Yabe, Masato Motomura
A Study of Channeled DRAM Memory Architectures. ICCD (2000)