Ke Wang

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 13

Top Topics

Energy Efficient

Reconfigurable Architecture

Convolutional Network

Network On Chip

Top Venues

IEEE Trans. Sustain. Comput.

IEEE Trans. Parallel Distributed Syst.

Publications

Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri
Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. 9 (2) (2024)
Jiajun Li, Yuxuan Zhang, Hao Zheng, Ke Wang
FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations. ISCA (2023)
Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri
SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. 33 (11) (2022)
Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri
AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE (2022)
Yingnan Zhao, Ke Wang, Ahmed Louri
FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. ICCD (2022)
Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri
SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. 7 (3) (2022)
Hao Zheng, Ke Wang, Ahmed Louri
Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA (2021)
Hao Zheng, Ke Wang, Ahmed Louri
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC (2020)
Ke Wang, Ahmed Louri
CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. IEEE Trans. Parallel Distributed Syst. 31 (9) (2020)
Ke Wang, Hao Zheng, Ahmed Louri
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro 40 (5) (2020)
Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores. ISCA (2019)
Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin. DATE (2019)