Kazutaka Mori

Publication Activity (10 Years)

Years Active: 1998-2014
Publications (10 Years): 0

Top Topics

Write Operations

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Kazuyoshi Okamoto, Kazutaka Mori, Kazumasa Yanagisawa
A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. CICC (2011)
Tamotsu Miyake, Takeo Yamashita, Norikatsu Asari, Hideki Sekisaka, Tom Sakai, Kazuhiro Matsuura, Atsushi Wakahara, Hideyuki Takahashi, Tom Hiyama, Kazuhisa Miyamoto, Kazutaka Mori
Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. CICC (2001)
Kazutaka Mori, Ken'ichi Kikushima, Fumio Ootsuka, Shin'ichiro Mitani
A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's. CICC (1998)
Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori
TCAD/DA for MPU and ASIC Development. ASP-DAC (1998)