Joseph J. Sharkey

Publication Activity (10 Years)

Years Active: 2004-2008
Publications (10 Years): 0

Publications

Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev
Hiding Communication Delays in Clustered Microarchitectures. SBAC-PAD (2008)
Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev
Reducing register pressure in SMT processors through L2-miss-driven early register release. ACM Trans. Archit. Code Optim. 5 (3) (2008)
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
Selective Writeback: Reducing Register File Pressure and Energy Consumption. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. IEEE Trans. Computers 57 (1) (2008)
Joseph J. Sharkey, Dmitry V. Ponomarev
Exploiting Operand Availability for Efficient Simultaneous Multithreading. IEEE Trans. Computers 56 (2) (2007)
Joseph J. Sharkey, Dmitry V. Ponomarev
An L2-miss-driven early register deallocation for SMT processors. ICS (2007)
Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose
Evaluating design tradeoffs in on-chip power management for CMPs. ISLPED (2007)
Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal
Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. HiPC (2006)
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. PACT (2006)
Joseph J. Sharkey, Dmitry Ponomarev
Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. ICPP (2006)
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
Adaptive reorder buffers for SMT processors. PACT (2006)
Joseph J. Sharkey, Dmitry V. Ponomarev
Efficient instruction schedulers for SMT processors. HPCA (2006)
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
Instruction packing: Toward fast and energy-efficient instruction scheduling. ACM Trans. Archit. Code Optim. 3 (2) (2006)
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal
Address-Value Decoupling for Early Register Deallocation. ICPP (2006)
Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose
Selective writeback: exploiting transient values for energy-efficiency and performance. ISLPED (2006)
Joseph J. Sharkey, Dmitry V. Ponomarev
Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. Euro-Par (2005)
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
Instruction packing: reducing power and delay of the dynamic scheduling logic. ISLPED (2005)
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
Power-Efficient Wakeup Tag Broadcast. ICCD (2005)
Joseph J. Sharkey, Dmitry V. Ponomarev
Non-uniform Instruction Scheduling. Euro-Par (2005)
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. PACS (2004)