João Navarro Jr.

Publication Activity (10 Years)

Years Active: 1995-2011
Publications (10 Years): 0

Publications

João Navarro Jr., Gustavo C. Martins
Design of high speed digital circuits with E-TSPC cell library. SBCCI (2011)
Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.
A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. SBCCI (2007)
Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
A 4.1 GHz prescaler using double data throughput E-TSPC structures. SBCCI (2007)
Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. ISCAS (2007)
Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije
Mismatch effect analyses in CMOS tapered buffers. ISCAS (2006)
Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije
A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI (2005)
Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. SBCCI (2004)
João Navarro Jr., Wilhelmus A. M. Van Noije
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
João Navarro Jr., Wilhelmus A. M. Van Noije
Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology. Great Lakes Symposium on VLSI (1998)
João Navarro Jr., Wilhelmus A. M. Van Noije
CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. Great Lakes Symposium on VLSI (1998)
João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije
A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems. Great Lakes Symposium on VLSI (1997)
Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.
Precise final state determination of mismatched CMOS latches. IEEE J. Solid State Circuits 30 (5) (1995)