A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.

Fernando P. H. de Miranda João Navarro Jr.Wilhelmus A. M. Van Noije

Published in: SBCCI (2004)

Keyphrases

cmos technology
low power
power consumption
high speed
clock frequency
low voltage
spl times
parallel processing
low cost
power dissipation
mixed signal
design considerations
image sensor
flip flops