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Jingcheng Tao
ORCID
Publication Activity (10 Years)
Years Active: 2018-2021
Publications (10 Years): 5
Top Topics
Random Sampling
High Frequency
Subband
Multi Band
Top Venues
A-SSCC
IEEE Trans. Circuits Syst. I Regul. Pap.
IEEE Trans. Circuits Syst. II Express Briefs
VLSI Circuits
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Publications
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Hanyang Su
,
Jingcheng Tao
,
Siegfred D. Balon
,
Chun-Huat Heng
A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp.
IEEE J. Solid State Circuits
56 (11) (2021)
Jingcheng Tao
,
Chun-Huat Heng
ΔΣ Fractional-N PLL With Hybrid IIR Noise Filtering.
IEEE Trans. Circuits Syst. II Express Briefs
(6) (2020)
Jingcheng Tao
,
Chun-Huat Heng
A 2.2-GHz 3.2-mW DTC-Free Sampling ΔΣ Fractional-N PLL With -110-dBc/Hz In-Band Phase Noise and -246-dB FoM and -83-dBc Reference Spur.
IEEE Trans. Circuits Syst. I Regul. Pap.
(9) (2019)
Jingcheng Tao
,
Chun-Huat Heng
A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur.
VLSI Circuits
(2019)
Jingcheng Tao
,
Chun-Huat Heng
A 1.6-GHz 3.3-mW 1.5-MHz Wide Bandwidth ΔΣ Fractional-N PLL with a Single Path FIR Phase Noise Filtering.
A-SSCC
(2018)