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A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp.

Hanyang SuJingcheng TaoSiegfred D. BalonChun-Huat Heng
Published in: IEEE J. Solid State Circuits (2021)
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