Jian Luo

Publication Activity (10 Years)

Years Active: 2018-2020
Publications (10 Years): 7

Top Topics

Cmos Technology

Analog To Digital Converter

Arc Consistency

Top Venues

J. Circuits Syst. Comput.

IEEE Trans. Circuits Syst. I Fundam. Theory Appl.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Jian Luo, Yang Liu, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Qi Yu
A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (4) (2020)
Jian Luo, Jing Li, Ning Ning, Kejun Wu, Zhen Liu, Yang Liu, Qi Yu
A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC. ISCAS (2019)
Jing Li, Xin Ye, Jian Luo, Ning Ning, Qi Yu
A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs. J. Circuits Syst. Comput. 28 (6) (2019)
Jian Luo, Jing Li, Shuangyi Wu, Ning Ning, Yang Liu
A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters. J. Circuits Syst. Comput. 28 (6) (2019)
Jing Li, Jian Luo, Yongfeng Ding, Ning Ning
A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter. APCCAS (2018)
Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction. IEEE Access 6 (2018)
Jian Luo, Jing Li, Ning Ning, Yang Liu, Qi Yu
A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)