A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter.

Jing Li Jian Luo Yongfeng Ding Ning Ning

Published in: APCCAS (2018)

Keyphrases

high speed
duty cycle
noisy data
missing data
analog circuits
noise reduction
power consumption
signal to noise ratio
noise level
additive noise
neural network
image processing
clustering algorithm
denoising
significantly reduced