Jayaram Bhasker

Publication Activity (10 Years)

Years Active: 1986-2004
Publications (10 Years): 0

Publications

Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden
Improving Design and Verification Productivity with VHDL-200x. DATE (2004)
Muhammad K. Dhodhi, Frank H. Hielscher, Robert H. Storer, Jayaram Bhasker
Datapath synthesis using a problem-space genetic algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (8) (1995)
Jayaram Bhasker, Tariq Samad, Douglas B. West
Size, chromatic number, and connectivity. Graphs Comb. 10 (2-4) (1994)
Rolf Ernst, Jayaram Bhasker
Simulation-Based Verification for High-Level Synthesis. IEEE Des. Test Comput. 8 (1) (1991)
Jayaram Bhasker, Huan-Chih Lee
An Optimizer for Hardware Synthesis. IEEE Des. Test Comput. 7 (5) (1990)
Jayaram Bhasker, Sartaj Sahni
Via Assignment in Single-Row Routing. IEEE Trans. Computers 38 (1) (1989)
Jayaram Bhasker
Implementation of an optimizing compiler for VHDL. ACM SIGPLAN Notices 23 (1) (1988)
Jayaram Bhasker
Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis. Softw. Pract. Exp. 18 (5) (1988)
Jayaram Bhasker, Sartaj Sahni
A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph. Algorithmica 3 (1988)
Jayaram Bhasker, Sartaj Sahni
A linear time algorithm to check for the existence of a rectangular dual of a planar triangulated graph. Networks 17 (3) (1987)
Jayaram Bhasker
An algorithm for microcode compaction of VHDL behavioral descriptions. MICRO (1987)
Jayaram Bhasker, Tariq Samad
Compacting MIMOLA microcode. MICRO (1987)
Jayaram Bhasker, Sartaj Sahni
A linear algorithm to find a rectangular dual of a planar triangulated graph. DAC (1986)
Jayaram Bhasker, Sartaj Sahni
Via Assignment in Single Row Routing. FSTTCS (1986)