James H. Mulligan Jr.

Publication Activity (10 Years)

Years Active: 1959-1997
Publications (10 Years): 0

Publications

Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (1) (1997)
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS (1995)
Ramon S. Co, James H. Mulligan Jr.
Optimization of phase-locked loop performance in data recovery systems. IEEE J. Solid State Circuits 29 (9) (1994)
Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.
Multiple training concept for back-propagation neural networks for use in associative memories. Neural Networks 6 (8) (1993)
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS (1993)
Eby G. Friedman, James H. Mulligan Jr.
Clock frequency and latency in synchronous digital systems. IEEE Trans. Signal Process. 39 (4) (1991)
Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.
Guaranteed recall of all training pairs for bidirectional associative memory. IEEE Trans. Neural Networks 2 (6) (1991)
Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.
On multiple training for bidirectional associative memory. IEEE Trans. Neural Networks 1 (3) (1990)
Yeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.
Two coding strategies for bidirectional associative memory. IEEE Trans. Neural Networks 1 (1) (1990)
James H. Mulligan Jr.
A Figure of Merit for Single-Pass Data Recording Systems. IRE Trans. Electron. Comput. 8 (1) (1959)