J. B. Kuo

Publication Activity (10 Years)

Years Active: 2002-2014
Publications (10 Years): 0

Top Topics

Multiresolution

Top Venues

Publications

D. H. Lung, S. K. Hu, J. B. Kuo, D. Chen, Y. J. Chen
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device. ISIC (2014)
H. J. Hung, J. B. Kuo, D. Chen, Chih-Sheng Yeh
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect. Microelectron. Reliab. 50 (5) (2010)
B. Chung, J. B. Kuo
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application. Integr. 41 (1) (2008)
B. Chung, J. B. Kuo
Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology. ISCAS (2006)
B. Chung, J. B. Kuo
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. PATMOS (2006)
G. Y. Liu, N. C. Wang, J. B. Kuo
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications. ISCAS (5) (2005)
E. Shen, J. B. Kuo
0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems. ISCAS (4) (2002)