Hyunmyung Oh

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 10

Top Topics

Discussion Groups

Integer Arithmetic

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Eunhwan Kim, Hyunmyung Oh, Jehun Lee, Jihoon Park, Myeongeun Kwon, Jae-Joon Kim
A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions. CICC (2024)
Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. DAC (2023)
Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim
A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim
TAIM: ternary activation in-memory computing hardware with 6T SRAM array. DAC (2022)
Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. A-SSCC (2021)
Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park, Jae-Joon Kim
Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. AICAS (2021)
Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. DATE (2021)
Daehyun Ahn, Hyunmyung Oh, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim
Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. IEEE Access 9 (2021)
Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. ICCAD (2020)
Woojin Park, Hyun Jong Yang, Hyunmyung Oh
Sum rates of asynchronous GFDMA and SC-FDMA for 5G uplink. ICT Express 1 (3) (2015)