Hung Tien Bui

Publication Activity (10 Years)

Years Active: 2001-2013
Publications (10 Years): 0

Top Topics

Parallel Architecture

Prediction Algorithm

Low Power Consumption

Analog To Digital Converter

Top Venues

Publications

Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer
Design of low power 4-bit flash ADC based on standard cells. NEWCAS (2013)
Hung Tien Bui
Pipelined FPGA design of the Goertzel algorithm for exon prediction. ISCAS (2012)
Michel Voyer, Sylvain-Robert Rivard, Luc Morin, Hung Tien Bui
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction. ISCAS (2011)
Jogendra Singh Thongam, Pierre Bouchard, Valentin Giurgiu, Hung Tien Bui, Mohand A. Ouhrouche
Sensorless vector control of PMSG for variable speed wind energy applications. CCECE (2010)
Marcel Siadjine Njinowa, Hung Tien Bui, François R. Boyer
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). ISCAS (2010)
Hung Tien Bui, Yvon Savaria
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2008)
Hung Tien Bui
High speed CDR using a novel binary phase detector with probable-lock-detection. ICECS (2008)
Hung Tien Bui
Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. ISCAS (2008)
Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS (2007)
Hung Tien Bui, Yvon Savaria
High speed differential pulse-width control loop based on frequency-to-voltage converters. ACM Great Lakes Symposium on VLSI (2006)
Hung Tien Bui
Dual-Path and Diode-Tracking Active Inductors for MCML Gates. CCECE (2006)
Hung Tien Bui, Yvon Savaria
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. IWSOC (2005)
Hung Tien Bui, Yvon Savaria
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. ISCAS (4) (2004)
Hung Tien Bui, Yvon Savaria
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. IWSOC (2004)
Abdulkarim Al-Sheraidah, Bassem Alhalabi, Hung Tien Bui
Five new high-performance multiplexer-based 1-bit full adder cells. ICECS (2001)