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10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.

Hung Tien BuiYvon Savaria
Published in: IWSOC (2004)
Keyphrases
  • high speed
  • low cost
  • phase difference
  • neural network
  • power consumption
  • low power
  • analog vlsi
  • detection algorithm