Hossein Valavi

Publication Activity (10 Years)

Years Active: 2018-2022
Publications (10 Years): 12

Top Topics

Variational Bayesian

Item Recommendation

Top Venues

IEEE J. Solid State Circuits

Publications

Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing. IEEE J. Solid State Circuits 57 (1) (2022)
Hongyang Jia, Murat Ozatay, Yinqi Tang, Hossein Valavi, Rakshit Pathak, Jinseok Lee, Naveen Verma
A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing. ISSCC (2021)
Jinseok Lee, Hossein Valavi, Yinqi Tang, Naveen Verma
Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. VLSI Circuits (2021)
Hossein Valavi, Sulin Liu, Peter J. Ramadge
Revisiting the Landscape of Matrix Factorization. AISTATS (2020)
Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing. IEEE J. Solid State Circuits 55 (9) (2020)
Hossein Valavi, Sulin Liu, Peter J. Ramadge
The Landscape of Matrix Factorization Revisited. CoRR (2020)
Hossein Valavi, Peter J. Ramadge
Multi-dataset Low-rank Matrix Factorization. CISS (2019)
Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma
A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute. IEEE J. Solid State Circuits 54 (6) (2019)
Hongyang Jia, Hossein Valavi, Yinqi Tang, Jintao Zhang, Naveen Verma
A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing. Hot Chips Symposium (2019)
Hossein Valavi, Peter J. Ramadge
An Upper-Bound on the Required Size of a Neural Network Classifier. ICASSP (2018)
Hongyang Jia, Yinqi Tang, Hossein Valavi, Jintao Zhang, Naveen Verma
A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing. CoRR (2018)
Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. VLSI Circuits (2018)