A Microprocessor implemented in 65nm CMOS with Configurable and Bit-scalable Accelerator for Programmable In-memory Computing.
Hongyang JiaYinqi TangHossein ValaviJintao ZhangNaveen VermaPublished in: CoRR (2018)
Keyphrases
- analog to digital converter
- random access memory
- embedded dram
- silicon on insulator
- high speed
- low cost
- circuit design
- nm technology
- power consumption
- single chip
- general purpose
- limited memory
- dynamic random access memory
- low voltage
- cmos technology
- low power
- compute intensive
- design considerations
- memory space
- low memory
- hash table
- image sensor
- chip design
- processor core
- random access
- main memory