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Honglan Zhan
ORCID
Publication Activity (10 Years)
Years Active: 2020-2023
Publications (10 Years): 6
Top Topics
Behavior Analysis
Content Addressable Memory
Hw Sw
Foreground Segmentation
Top Venues
DATE
IEEE J. Solid State Circuits
PACT
IEEE Trans. Very Large Scale Integr. Syst.
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Publications
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Hongwei Cui
,
Yujie Cui
,
Honglan Zhan
,
Shuhao Liang
,
Xianhua Liu
,
Chun Yang
,
Xu Cheng
MBAPIS: Multi-Level Behavior Analysis Guided Program Interval Selection for Microarchitecture Studies.
PACT
(2023)
Hongwei Cui
,
Shuhao Liang
,
Yujie Cui
,
Weiqi Zhang
,
Honglan Zhan
,
Chun Yang
,
Xianhua Liu
,
Xu Cheng
A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture Evaluation.
DATE
(2023)
Honglan Zhan
,
Chenxi Wang
,
Hongwei Cui
,
Xianhua Liu
,
Feng Liu
,
Xu Cheng
High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port Operation.
DATE
(2023)
Zhiting Lin
,
Honglan Zhan
,
Zhongwei Chen
,
Chunyu Peng
,
Xiulong Wu
,
Wenjuan Lu
,
Qiang Zhao
,
Xuan Li
,
Junning Chen
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing.
IEEE J. Solid State Circuits
56 (8) (2021)
Zhiting Lin
,
Zhiyong Zhu
,
Honglan Zhan
,
Chunyu Peng
,
Xiulong Wu
,
Yuan Yao
,
Jianchao Niu
,
Junning Chen
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports.
IEEE J. Solid State Circuits
56 (9) (2021)
Zhiting Lin
,
Honglan Zhan
,
Xuan Li
,
Chunyu Peng
,
Wenjuan Lu
,
Xiulong Wu
,
Junning Chen
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands.
IEEE Trans. Very Large Scale Integr. Syst.
28 (5) (2020)