Hans Eveking

Publication Activity (10 Years)

Years Active: 1987-2011
Publications (10 Years): 0

Publications

Tobias Dornes, Martin Schweikert, Hans Eveking
Analyse von Gegenbeispielen bei Verifikation mit unvollständigen Eigenschaftssätzen. MBMV (2011)
Martin Schweikert, Tobias Dornes, Hans Eveking
Erzeugung von Operationseigenschaften aus UML Sequenzdiagrammen. MBMV (2011)
Hans Eveking, Tobias Dornes, Martin Schweikert
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. HLDVT (2011)
Martin Schweikert, Hans Eveking
Verwendung von UML Sequenzdiagrammen zur Spezifikation und Generierung von RTL Eigenschaftssätzen. MBMV (2010)
Tobias Dornes, Hans Eveking
Formale Verifikation von Systemeigenschaften unter Verwendung normalisierter formaler Spezifikationen. MBMV (2010)
Martin Oberkönig, Martin Schickel, Hans Eveking
Quantitative Qualitätsaussagen über Testbenches mittels formaler Eigenschaften. MBMV (2009)
Martin Oberkönig, Martin Schickel, Hans Eveking
Eine quantitative Vollständigkeitsanalyse für Eigenschaftssätze. MBMV (2008)
Martin Braun, Minh D. Nguyen, Hans Eveking, Martin Schickel, Wolfgang Kunz
Methoden zur Verifikation von Kommunikationsstrukturen. MBMV (2007)
Hans Eveking, Martin Braun, Martin Schickel, Martin Schweikert, Volker Nimbler
Multi-Level Assertion-Based Design. MEMOCODE (2007)
Martin Schickel, Martin Oberkönig, Martin Schweikert, Hans Eveking
A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Set. FDL (2007)
Martin Oberkönig, Martin Schickel, Hans Eveking
A Quantitative Completeness Analysis for Property-Sets. FMCAD (2007)
Martin Schickel, Volker Nimbler, Martin Braun, Hans Eveking
On Consistency and Completeness of Property-Sets. FDL (2006)
Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter
Symbolic simulation techniques-state-of-the-art and applications. HLDVT (2001)
Hans Eveking
Formale Verifikationsverfahren (Formal Verification). Informationstechnik Tech. Inform. 43 (1) (2001)
Claudia Blank, Gerd Ritter, Holger Hinrichsen, Hans Eveking
Formale Verifikation der Register-Allokation. MBMV (2000)
Holger Hinrichsen, Gerd Ritter, Hans Eveking
Automatische Synthese und Verifikation von RISC-Prozessoren. MBMV (1999)
Hans Eveking, Holger Hinrichsen, Gerd Ritter
Automatic Verification of Scheduling Results in High-Level Synthesis. DATE (1999)
Gerd Ritter, Holger Hinrichsen, Hans Eveking
Formal Verification of Descriptions with Distinct Order of Memory Operations. ASIAN (1999)
Gerd Ritter, Hans Eveking, Holger Hinrichsen
Formal Verification of Designs with Complex Control by Symbolic Simulation. CHARME (1999)
Hans Eveking
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems. EURO-DAC (1994)
Hans Eveking, Stefan Höreth
Optimization and Resynthesis of Complex Data-Paths. DAC (1993)
Hans Eveking, Christoph Mai
Formal verification of timing conditions. EURO-DAC (1990)
Hans Eveking
Automatic Verification of Extensions of Hardware Descriptions. CAV (DIMACS/AMS volume) (1990)
Hans Eveking
Automatic Verification of Extensions of Hardware Descriptions. CAV (1990)
Hans Eveking
Formal reasoning about switch-level MOS descriptions. Microprocess. Microprogramming 21 (1-5) (1987)