Grzegorz Pastuszak

Publication Activity (10 Years)

Years Active: 2004-2021
Publications (10 Years): 8

Top Topics

Intra Prediction

Stereo Matching

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

J. Real Time Image Process.

Publications

Grzegorz Pastuszak, Adam Skowyrski, Andrzej Jamiolkowski
Quantifier elimination theory and maps which preserve semipositivity. Quantum Inf. Process. 20 (3) (2021)
Grzegorz Pastuszak
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. IEEE Trans. Very Large Scale Integr. Syst. 28 (12) (2020)
Grzegorz Pastuszak
Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2020)
Grzegorz Pastuszak, Andrzej Abramowski
Algorithm and Architecture Design of the H.265/HEVC Intra Encoder. IEEE Trans. Circuits Syst. Video Technol. 26 (1) (2016)
Grzegorz Pastuszak, Takeo Kamizawa, Andrzej Jamiolkowski
On a Criterion for Simultaneous Block-Diagonalization of Normal Matrices. Open Syst. Inf. Dyn. 23 (1) (2016)
Grzegorz Pastuszak, Maciej Trochimiuk
Algorithm and architecture design of the motion estimation for the H.265/HEVC 4K-UHD encoder. J. Real Time Image Process. 12 (2) (2016)
Grzegorz Pastuszak, Mariusz H. Jakubowski
Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder. J. Signal Process. Syst. 82 (3) (2016)
Grzegorz Pastuszak, Maciej Trochimiuk
Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder. J. Real Time Image Process. 11 (4) (2016)
Grzegorz Pastuszak
Flexible Architecture Design for H.265/HEVC Inverse Transform. Circuits Syst. Signal Process. 34 (6) (2015)
Grzegorz Pastuszak
Hardware architectures for the H.265/HEVC discrete cosine transform. IET Image Process. 9 (6) (2015)
Grzegorz Pastuszak
Architecture Design of the H.264/AVC Encoder Based on Rate-Distortion Optimization. IEEE Trans. Circuits Syst. Video Technol. 25 (11) (2015)
Mikolaj Roszkowski, Grzegorz Pastuszak
Intra Prediction for the Hardware H.264/AVC High Profile Encoder. J. Signal Process. Syst. 76 (1) (2014)
Andrzej Abramowski, Grzegorz Pastuszak
A double-path intra prediction architecture for the hardware H.265/HEVC encoder. DDECS (2014)
Grzegorz Pastuszak
FPGA architectures of the quantization and the dequantization for video encoders. DDECS (2014)
Mikolaj Roszkowski, Grzegorz Pastuszak
FPGA design of the computation unit for the semi-global stereo matching algorithm. DDECS (2014)
Andrzej Abramowski, Grzegorz Pastuszak
A Novel Intra Prediction Architecture for the Hardware HEVC Encoder. DSD (2013)
Grzegorz Pastuszak, Maciej Trochimiuk
Architecture Design and Efficiency Evaluation for the High-Throughput Interpolation in the HEVC Encoder. DSD (2013)
Grzegorz Pastuszak, Mariusz H. Jakubowski
Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder. IEEE Trans. Circuits Syst. Video Technol. 23 (5) (2013)
Grzegorz Pastuszak, Mariusz H. Jakubowski
Hardware implementation of adaptive motion estimation and compensation for H.264/AVC. PCS (2012)
Grzegorz Pastuszak, Michal Wieczorek
Stream header decoder and context-adaptive variable-length decoder hardware module for H.264/AVC codec. PDeS (2010)
Mikolaj Roszkowski, Grzegorz Pastuszak
Intra prediction hardware module for high-profile H.264/AVC decoder. PDeS (2010)
Andrzej Abramowski, Grzegorz Pastuszak
Context-adaptive binary arithmetic decoder architecture for H.264/AVC. PDeS (2010)
Grzegorz Brzuchalski, Grzegorz Pastuszak
Hardware implementation of the transformation module of the MPEG-4 AAC standard. PDeS (2010)
Mariusz H. Jakubowski, Grzegorz Pastuszak
Data Reuse in Two-level Hierarchical Motion Estimation for High Resolution Video Coding. SIGMAP (2010)
Mariusz H. Jakubowski, Grzegorz Pastuszak
An Adaptive Computation-aware Algorithm for Multi-frame Variable Block-size Motion Estimation in H.264/AVC. SIGMAP (2009)
Grzegorz Pastuszak
A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC. IEEE Trans. Circuits Syst. Video Technol. 18 (7) (2008)
Grzegorz Pastuszak
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection. ISVLSI (2008)
Mariusz H. Jakubowski, João Ascenso, Grzegorz Pastuszak
Constant Bitrate Control for a Distributed Video Coding System. SIGMAP (2008)
Andrzej Pietrasiewicz, Grzegorz Pastuszak
Rate Control for Multi-Sequence H.264/AVC Compression. SIGMAP (2007)
Grzegorz Pastuszak, Andrzej Pietrasiewicz
Multi-sequence H.264/AVC Rate Control Based on the Linear Model. ICETE (Selected Papers) (2007)
Grzegorz Pastuszak
Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression. SiPS (2007)
Grzegorz Pastuszak
Architecture Design for the Context Formatter in the H.264/AVC Encoder. DDECS (2006)
Grzegorz Pastuszak
Parallel Symbol Architectures for H.264/AVC Binary Coder Based on Arithmetic Coding. PARELEC (2006)
Grzegorz Pastuszak
A high-performance architecture for embedded block coding in JPEG 2000. IEEE Trans. Circuits Syst. Video Technol. 15 (9) (2005)
Grzegorz Pastuszak
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000. ICME (2005)
Grzegorz Pastuszak
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder. ICIAP (2005)
Grzegorz Pastuszak
Hardware-Oriented Analysis of the Arithmetic Coding - Comparative Study of JPEG2000 and H.264/AVC Compression Standards. ICETE (3) (2004)
Grzegorz Pastuszak
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding. PARELEC (2004)
Grzegorz Pastuszak
A high-performance architecture of arithmetic coder in JPEG2000. ICME (2004)