Hardware architectures for the H.265/HEVC discrete cosine transform.

Grzegorz Pastuszak

Published in: IET Image Process. (2015)

Keyphrases

discrete cosine transform
hardware architectures
video coding standard
image compression
transform domain

computational power
hardware architecture
dct coefficients
video codec
filter bank

compressed images
intra prediction
dct domain
image blocks
jpeg images

video compression
spatial domain
discrete fourier transform
fast fourier transform
machine learning