Gordon B. Steven

Publication Activity (10 Years)

Years Active: 1988-2003
Publications (10 Years): 0

Publications

Colin Egan, Gordon B. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan
Two-level branch prediction using neural networks. J. Syst. Archit. 49 (12-15) (2003)
Colin Egan, Gordon B. Steven, Lucian N. Vintan
Cached Two-Level Adaptive Branch Predictors with Multiple Stages. ARCS (2002)
Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan
Applying Caching to Two-Level Adaptive Branch Prediction. DSD (2001)
Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan
Dynamic Branch Prediction Using Neural Networks. DSD (2001)
Fleur L. Steven, Colin Egan, Richard D. Potter, Gordon B. Steven
Adding static data dependence collapsing to a high-performance instruction scheduler. J. Syst. Archit. 47 (8) (2001)
Daniel Tate, Gordon B. Steven, Fleur L. Steven
Static Scheduling for Out-of-order Instruction Issue Processors. ACAC (2000)
Lucian N. Vintan, Cristian Armat, Gordon B. Steven
The impact of cache organisation on the instruction issue rate of a superscalar processor. PDP (1999)
Daniel Tate, Gordon B. Steven, Paul A. Findlay
The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. EUROMICRO (1998)
Gordon B. Steven, Bruce Christianson, Roger Collins, Richard D. Potter, Fleur L. Steven
A superscalar architecture to exploit instruction level parallelism. Microprocess. Microsystems 20 (7) (1997)
Roger Collins, Gordon B. Steven
Instruction Scheduling for a Superscalar Architecture. EUROMICRO (1996)
Richard D. Potter, Gordon B. Steven
Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture. Euro-Par, Vol. II (1996)
C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven
Hades-towards the design of an asynchronous superscalar processor. ASYNC (1995)
Rod Adams, Sue M. Gray, Gordon B. Steven
Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler. PDP (1994)
Roger Collins, Gordon B. Steven
An explicitly declared delayed-branch mechanism for a superscalar architecture. Microprocess. Microprogramming 40 (10-12) (1994)
Gordon B. Steven, Fleur L. Steven
ALU design and processor branch architecture. Microprocess. Microprogramming 36 (5) (1993)
Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale
Addressing mechanisms for VLIW and superscalar processors. Microprocess. Microprogramming 39 (2-5) (1993)
Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven
Static instruction scheduling for the HARP multiple-instruction-issue architecture. Microprocess. Microsystems 17 (7) (1993)
Rod Adams, Gordon B. Steven
A parallel pipelined processor with conditional instruction execution. SIGARCH Comput. Archit. News 19 (1) (1991)
R. G. Adams, Sue M. Gray, Gordon B. Steven
Utilising low level parallelism in general purpose code: the HARP project. Microprocessing and Microprogramming 29 (3) (1990)
Fleur L. Williams, Gordon B. Steven
Address and data register separation on the M68000 family. SIGARCH Comput. Archit. News 18 (2) (1990)
Fleur L. Williams, Gordon B. Steven
How useful are complex instructions? A case study using the M68000. Microprocessing and Microprogramming 29 (4) (1990)
Gordon B. Steven, Sue M. Gray, R. G. Adams
HARP: A parallel pipelined RISC processor. Microprocess. Microsystems 13 (9) (1989)
Gordon B. Steven
A novel effective address calculation mechanism for RISC microprocessors. SIGARCH Comput. Archit. News 16 (4) (1988)
Gordon B. Steven, Fleur L. Williams
General addressing mechanisms for microprocessors. Microprocess. Microsystems 12 (2) (1988)