The impact of cache organisation on the instruction issue rate of a superscalar processor.
Lucian N. VintanCristian ArmatGordon B. StevenPublished in: PDP (1999)
Keyphrases
- instruction set
- memory hierarchy
- memory subsystem
- computer architecture
- memory access
- cache misses
- multithreading
- floating point
- computing power
- application specific
- level parallelism
- data access
- prefetching
- query processing
- ibm power processor
- embedded systems
- main memory
- computational power
- database management systems
- parallel computing
- coarse grained
- highly efficient
- computer systems
- embedded processors
- knowledge management
- database systems
- shared memory multiprocessors