Gopalakrishnan Lakshminarayanan

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 23

Top Topics

Fourier Transform

Elimination Algorithm

Top Venues

IET Comput. Digit. Tech.

Microprocess. Microsystems

Publications

Raja Sekar Kumaresan, Marshal Raj, Gopalakrishnan Lakshminarayanan
Framework for QCA Layout Generation and Rules for Rotated Cell Design. J. Circuits Syst. Comput. 32 (7) (2023)
Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
SaHNoC: an optimal energy efficient hybrid networks-on-chip architecture. J. Supercomput. 79 (6) (2023)
Parameshwaran Ramalingam, R. Thanuja, R. Bhavani, Gopalakrishnan Lakshminarayanan
An Efficient Lossless Telemetry Data Compression and Fault Analysis System Using 2SMLZ and CMOW-DLNN. Wirel. Pers. Commun. 127 (3) (2022)
Parameshwaran Ramalingam, Abolfazl Mehbodniya, Julian Webber, Mohammad Shabaz, Gopalakrishnan Lakshminarayanan
Telemetry Data Compression Algorithm Using Balanced Recurrent Neural Network and Deep Learning. Comput. Intell. Neurosci. 2022 (2022)
Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
SMA: A constructive partitioning based mapping approach for Networks-on-Chip. Microprocess. Microsystems 94 (2022)
Aravindhan Alagarsamy, Sundarakannan Mahilmaran, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
FRDS: An efficient unique on-Chip interconnection network architecture. Integr. 87 (2022)
Parameshwaran Ramalingam, Gopalakrishnan Lakshminarayanan, Manikandan Ramachandran, Rizwan Patan
Kinematic adaptive frequency sampling combined spatio temporal features for snow monitoring in aerospace applications. Expert Syst. Appl. 184 (2021)
Mohammadreza Asadikouhanjani, Hao Zhang, Gopalakrishnan Lakshminarayanan, Hyuk-Jae Lee, Seok-Bum Ko
A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Bibin Sam Paul S, Antony Xavier Glittas, Gopalakrishnan Lakshminarayanan
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition. Integr. 76 (2021)
Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology. IET Comput. Digit. Tech. 15 (3) (2021)
R. Umamaheswaran, Parameshwaran Ramalingam, Marshal Raj, Gopalakrishnan Lakshminarayanan, S. Thiruppathirajan
A novel boundary elemental analysis based frequency domain adaptive sampling technique for aerospace application. Microprocess. Microsystems 83 (2021)
Raja Sekar Kumaresan, Marshal Raj, Gopalakrishnan Lakshminarayanan
Area-Efficient D-Flip Flop and XOR in QCA. ICCCNT (2020)
Marshal Raj, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko, Nagi Naganathan, N. Ramasubramanian
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems. IEEE Embed. Syst. Lett. 12 (4) (2020)
Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan
High Speed Controllable Inverter for Adder-Subtractor in QCA. ICCCNT (2019)
Geethu Sathees Babu, Lakshmi Renuka Madala, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
Low-complex processing element architecture for successive cancellation decoder. Integr. 66 (2019)
Aravindhan Alagarsamy, Gopalakrishnan Lakshminarayanan, Seok-Bum Ko
KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC. IET Comput. Digit. Tech. 13 (4) (2019)
Geethu Sathees Babu, Gopalakrishnan Lakshminarayanan
Reconfigurable address generator for multi-standard interleaver. Microprocess. Microsystems 65 (2019)
Marshal Raj, Raja Sekar Kumaresan, Gopalakrishnan Lakshminarayanan
Optimized Multiplexer and Exor gate in 4-dot 2-electron QCA using Novel Input Technique. ICCCNT (2019)
Aravindhan Alagarsamy, Gopalakrishnan Lakshminarayanan, Sundarakannan Mahilmaran, Seok-Bum Ko
A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption. IEEE Access 7 (2019)
Nithish Kumar Venkatachalam, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios. IET Comput. Digit. Tech. 10 (2) (2016)
Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan
Two-parallel pipelined fast Fourier transform processors for real-valued signals. IET Circuits Devices Syst. 10 (4) (2016)
Venkatachalam Nithish Kumar, Koteswara Rao Nalluri, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio. J. Low Power Electron. 11 (2) (2015)
Antony Xavier Glittas, Gopalakrishnan Lakshminarayanan
Pipelined FFT architectures for real-time signal processing and wireless communication applications. VDAT (2014)
Venkatachalam Nithish Kumar, Pani Prithvi Raj, Gopalakrishnan Lakshminarayanan, Mathini Sellathurai
Low Power and Area Efficient Carry Select Adder. J. Low Power Electron. 10 (4) (2014)
Deepa N. Sarma, Gopalakrishnan Lakshminarayanan, K. V. R. Suryakiran Chavali
A Novel Encoding Scheme for Low Power in Network on Chip Links. VLSI Design (2012)
Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. VLSI Design 2008 (2008)
G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan
Automation techniques for implementation of hybrid wave-pipelined 2D DWT. J. Real Time Image Process. 3 (3) (2008)
Gopalakrishnan Lakshminarayanan, B. Venkataramani
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)