A Novel Encoding Scheme for Low Power in Network on Chip Links.

Deepa N. Sarma Gopalakrishnan Lakshminarayanan K. V. R. Suryakiran Chavali

Published in: VLSI Design (2012)

Keyphrases

encoding scheme
low power
network on chip
power dissipation
cmos technology
power consumption
low cost
high speed
single chip
routing algorithm
network simulator
genetic algorithm
digital signal processing
multi processor
image sensor
real time
data transfer
end to end
interconnection networks
pattern recognition