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G. Seetharaman
Publication Activity (10 Years)
Years Active: 2008-2018
Publications (10 Years): 1
Top Topics
Data Hiding
Error Correction
Reed Solomon
Low Delay
Top Venues
J. Electron. Test.
AHS
Microprocess. Microsystems
Int. J. Comput. Appl. Technol.
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Publications
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Jayshree
,
G. Seetharaman
Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay.
AHS
(2018)
M. Maheswari
,
G. Seetharaman
Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link.
J. Electron. Test.
30 (4) (2014)
M. Maheswari
,
G. Seetharaman
Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link.
Int. J. Comput. Appl. Technol.
49 (1) (2014)
M. Maheswari
,
G. Seetharaman
Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links.
Microprocess. Microsystems
37 (4-5) (2013)
V. Vireen
,
N. Venugopalachary
,
G. Seetharaman
,
B. Venkataramani
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.
VLSI Design
(2009)
G. Seetharaman
,
B. Venkataramani
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.
ACM Trans. Reconfigurable Technol. Syst.
2 (2) (2009)
G. Seetharaman
,
B. Venkataramani
,
Gopalakrishnan Lakshminarayanan
Automation techniques for implementation of hybrid wave-pipelined 2D DWT.
J. Real Time Image Process.
3 (3) (2008)