Eero Aho

Publication Activity (10 Years)

Years Active: 2002-2012
Publications (10 Years): 0

Top Topics

Autonomous Mobile

Collaborative Editing

Top Venues

Publications

Eero Aho, Kimmo Kuusilinna, Tomi Aarnio, Janne Pietiainen, Jari Nikara
Towards real-time applications in mobile web browsers. ESTIMedia (2012)
Claudio Brunelli, Eero Aho, Heikki Berg
OpenCL implementation of Cholesky matrix decomposition. SoC (2011)
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen
A Configurable Motion Estimation Architecture for Block-Matching Algorithms. IEEE Trans. Circuits Syst. Video Technol. 19 (4) (2009)
Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna
A case for multi-channel memories in video recording. DATE (2009)
Eero Aho, Kimmo Kuusilinna, Jari Nikara
Memory access characteristics of H.264 video encoder on embedded processor. SiPS (2009)
Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna
Performance analysis of multi-channel memories in mobile devices. SoC (2009)
Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna
A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms. IEEE Trans. Circuits Syst. Video Technol. 18 (4) (2008)
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
Configurable Data Memory for Multimedia Processing. J. Signal Process. Syst. 50 (2) (2008)
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
Configurable implementation of parallel memory based real-time video downscaler. Microprocess. Microsystems 31 (5) (2007)
Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 16 (7) (2006)
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
Parallel Memory Architecture for Arbitrary Stride Accesses. DDECS (2006)
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
Parallel Memory Implementation for Arbitrary Stride Accesses. ICSAMOS (2006)
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen
Comments on "Winscale: an image-scaling algorithm using an area pixel Model". IEEE Trans. Circuits Syst. Video Technol. 15 (3) (2005)
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen
Block-level parallel processing for scaling evenly divisible frames. ISCAS (2) (2005)
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
Block-level parallel processing for scaling evenly divisible images. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2005)
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen
Address Computation in Configurable Parallel Memory Architecture. IEICE Trans. Inf. Syst. (7) (2004)
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen
Enhanced Configurable Parallel Memory Architecture. DSD (2002)