Dongjun Park

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 12

Top Topics

Secure Communication

Countermeasures

Key Distribution

Top Venues

Publications

Daehyeon Bae, Dongjun Park, GyuSang Kim, Minsig Choi, Nayeon Lee, Heeseok Kim, Seokhie Hong
Autoscaled-Wavelet Convolutional Layer for Deep Learning-Based Side-Channel Analysis. IEEE Access 11 (2023)
Dongjun Park, Minsig Choi, GyuSang Kim, Daehyeon Bae, Heeseok Kim, Seokhie Hong
Stealing Keys From Hardware Wallets: A Single Trace Side-Channel Attack on Elliptic Curve Scalar Multiplication Without Profiling. IEEE Access 11 (2023)
Chang-Kyun Kim, Joonhwan Kim, Dongjun Park, Dong-Soo Kwon
Workspace Derivation of Arthroscope Using Morphological Data and Standard Portal Placement Method for Shoulder Arthroscopy. IEEE Access 9 (2021)
GyuSang Kim, Dongjun Park, HeeSeok Kim, Seokhie Hong
Side Channel Vulnerability in Parity Computation of Generic Key Reconciliation Process on QKD. ICTC (2021)
Dongjun Park, Geung-Hee Lee
Structured Pattern Pruning Using Regularization. CoRR (2021)
Dongjun Park, GyuSang Kim, Donghoe Heo, Suhri Kim, HeeSeok Kim, Seokhie Hong
Single trace side-channel attack on key reconciliation in quantum key distribution system and its efficient countermeasures. ICT Express 7 (1) (2021)
Dongjun Park, Jongsun Kim
A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL. Circuits Syst. Signal Process. 39 (4) (2020)
Dongjun Park, Jongsun Kim
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication. IEICE Electron. Express 17 (19) (2020)
Dongjun Park, Donghoe Heo, Suhri Kim, Seokhie Hong
Single Trace Attack on Key Reconciliation Process for Quantum Key Distribution. ICTC (2020)
Dongjun Park, Jongsun Kim
A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs. ISCAS (2018)
Dongjun Park, Junsub Yoon, Jongsun Kim
A low-power SerDes for high-speed on-chip networks. ISOCC (2017)
Dongjun Park, Geontae Park, Jongsun Kim
A 0.15 to 2.2 GHz all-digital delay-locked loop. NEWCAS (2017)