A low-power SerDes for high-speed on-chip networks.
Dongjun ParkJunsub YoonJongsun KimPublished in: ISOCC (2017)
Keyphrases
- low power
- high speed
- single chip
- low power consumption
- low cost
- mixed signal
- high power
- vlsi architecture
- cmos technology
- image sensor
- wireless transmission
- signal processor
- real time
- frame rate
- power reduction
- power consumption
- vlsi circuits
- nm technology
- logic circuits
- digital signal processing
- network structure
- gate array
- delay insensitive
- focal plane