Dong-Shong Liang

Publication Activity (10 Years)

Years Active: 2005-2012
Publications (10 Years): 0

Top Topics

Numerical Analysis

Top Venues

IEICE Trans. Electron.

Publications

Yen-Lin Pan, Cheng-Chi Tai, Dong-Shong Liang
Numerical Analysis of the Effect of Thin-Film Thickness and Material in Field Mapping of Eddy-Current Probes Using Photoinductive Technique. IEICE Trans. Electron. (1) (2012)
Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen
Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources. IEICE Trans. Inf. Syst. (8) (2010)
Kwang-Jow Gan, Dong-Shong Liang
Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit. IEICE Trans. Electron. (4) (2010)
Dong-Shong Liang, Kwang-Jow Gan, Cheng-Chi Tai, Cher-Shiung Tsai
Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio. IEICE Trans. Electron. (5) (2009)
Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen
Multiple-Valued Memory Design by Standard BiCMOS Technique. CSIE (3) (2009)
Dong-Shong Liang, Kwang-Jow Gan
New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits. DELTA (2008)
Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen
Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process. APCCAS (2006)
Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai
The Design of MOS-NDR-Based Cellular Neural Network. IJCNN (2006)
Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen
Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process. APCCAS (2006)
Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen
Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process. IWSOC (2005)
Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang
Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits. IWSOC (2005)
Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su
Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits. IWSOC (2005)