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Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio.
Dong-Shong Liang
Kwang-Jow Gan
Cheng-Chi Tai
Cher-Shiung Tsai
Published in:
IEICE Trans. Electron. (2009)
Keyphrases
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power reduction
circuit design
neural network
social networks
positive and negative
implementation issues
digital circuits
signal noise ratio
short circuit
peak detection
data sets
multiscale
efficient implementation
future development
electronic circuits
analog vlsi