Chung-Jay Yang

Publication Activity (10 Years)

Years Active: 2008-2013
Publications (10 Years): 0

Top Topics

Decoding Algorithm

Hardware Architecture

Low Density Parity Check

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Signal Process.

Publications

Yeong-Luh Ueng, Bo-Jhang Yang, Chung-Jay Yang, Huang-Chang Lee, Jeng-Da Yang
An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Yeong-Luh Ueng, Kuo-Hsuan Liao, Hsueh-Chih Chou, Chung-Jay Yang
A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA. IEEE Trans. Signal Process. 61 (11) (2013)
Yeong-Luh Ueng, Yu-Luen Wang, Li-Sheng Kan, Chung-Jay Yang, Yung-Hsiang Su
Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture. IEEE Trans. Signal Process. 60 (8) (2012)
Yeong-Luh Ueng, Chen-Yap Leong, Chung-Jay Yang, Chung-Chao Cheng, Kuo-Hsuan Liao, Shu-Wei Chen
An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2012)
Yu-Luen Wang, Yeong-Luh Ueng, Chien-Lien Peng, Chung-Jay Yang
Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2011)
Yeong-Luh Ueng, Chung-Jay Yang, Shu-Wei Chen, Wei-Xuan Wu
A selective-input non-binary LDPC decoder architecture. ISOCC (2011)
Yeong-Luh Ueng, Chung-Jay Yang, Kuan-Chieh Wang, Chun-Jung Chen
A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2010)
Yeong-Luh Ueng, Chung-Jay Yang, Chun-Jung Chen
A Shuffled Message-passing Decoding Method for Memory-based LDPC Decoders. ISCAS (2009)
Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang
VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. ISCAS (2008)